As CMOS technology advances through geometries and chip densities increase, the industry faces rising challenges in balancing chip performance and power requirements. The challenge is being addressed partly by making performance / power tradeoffs in product generations while various partial solutions are implemented. However, even the combined effects promise to be insufficient as industry advances process geometries beyond 65nm and electrical leakage at the gate level has moved up to unacceptable levels.

Silicon-on-Insulator was introduced at the 130 nm level and continues its adoption as a measure to boost transistor performance. However, SOI does not directly help in reducing gate leakage and cannot combat the exacerbation of this problem beyond 65nm.

Strain was introduced at the 90nm level and continues to be used, again for boosting transistor performance, specifically NMOS drive current. Strain also does not directly help in reducing gate leakage and cannot hold back this increasing problem.

Hybrid Orientation Technology - HOT is a newer technique that industry is exploring, with performance enhancement as the target. Again this technology cannot combat gate leakage.

High K Di-electrics and metal gates are intriguing solutions that industry is grooming for the future targeted to leakage reduction. However, the industry may once again face a tradeoff in applying their benefits fully, due to curbs on drive current enhancement that might accompany the benefits.


Benefits of MST™